1. Field of the Invention
The present invention relates to the field of semiconductor fabrication, and more particularly to a method and wafer for replacing costly starting material typically associated with advanced CMOS processes with a more economical starting material without sacrificing latchup immunity.
2. Description of the Relevant Art
Integrated circuits fabricated on semiconductor substrates are well known. In a typical MOS semiconductor process, a plurality of MOS transistors are fabricated in a silicon substrate through a series of photolithography, implant, oxidation, etch, and other well known semiconductor process steps. In a CMOS semiconductor process, n-channel and p-channel transistors are fabricated on a monolithic silicon substrate. Typically, the p-channel transistors are located within a n-type region of the silicon substrate while the n-channel transistors are located within a p-type portion of the silicon substrate.
To achieve maximum performance from the integrated circuit, it is typically desirable to fabricate the n-channel and p-channel transistors within a relatively lightly doped "well". Lightly doped wells decrease junction capacitances that reduce the response time of the transistor. Unfortunately, the requirement of producing n-channel transistors within a p-type region of the substrate and p-channel transistors within a n-type portion of the substrate results in the unintended formation of a pair of unwanted parasitic bipolar transistors. Under certain abnormal, but nevertheless frequently occurring, operating conditions, the cross-coupled parasitic transistors can be turned on. The arrangement of the pair of parasitic transistors forms an undesirable positive feedback loop that can result in a low impedance and potentially destructive path from the power supply (V.sub.DD) to ground.
Referring to FIG. 1 a simplified partial cross sectional view of a CMOS integrated circuit is shown. A vertical pnp bipolar transistor 101 is comprised of a p+ source/drain region 102, which serves as the emitter, n-well 104, which serves as the base, and in the embodiment shown in FIG. 1, a p-type epitaxial layer 106 formed over a p+ bulk 120 which serve as the collector of pnp transistor 101. The CMOS integrated circuit shown in FIG. 1 further includes a laterally oriented npn transistor 110 comprising a n+ source/drain region 112, which acts as the emitter of transistor 110, p-well region 114, which acts as the base, and n-well region 104, which acts as the collector. It will be appreciated that the collector of bipolar transistor 101 and the base of transistor 110 are located within p-type regions of the silicon wafer between which no significant potential barrier exists. Thus, the collector current i.sub.c2 of transistor 101 will act as a base current i.sub.b1 of transistor 110 in the absence of an alternative path to ground. If the base current i.sub.b1 of transistor 110 is sufficient to turn transistor 110 on, a current will flow from collector to emitter of transistor 110 thereby increasing the base current of transistor 101 which, in turn, increases the collector current i.sub.c2 and the base current i.sub.b1.
In this manner, it can be seen that the pair of coupled bipolar transistors 101 and 110 form a positive feedback mechanism which can result in extremely low impedance path from V.sub.DD resulting in a significant and unwanted power dissipation within the integrated circuit causing the silicon substrate to rise in temperature and potentially resulting in device failure. This phenomenon in CMOS integrated circuits is known as a latchup condition. Because CMOS integrated circuits are increasingly popular because of their potential for low power dissipation under normal operating circumstances, semiconductor manufacturers have devoted an enormous amount of energy to address and minimize the problems associated with the CMOS latchup. One effective method of improving an integrated circuit's immunity to latchup is to provide a low impedance path n the bulk or substrate of the silicon wafer to effectively shunt current that would otherwise participate as a base current into the laterally oriented transistor 110. Such a path is provided by a typically provided heavily doped p+ bulk region 120 as shown in FIG. 1. By reducing the substrate resistance r.sub.sub, the substrate current i.sub.sub is increased. An increase in the substrate current i.sub.sub results in a lower base current i.sub.b1, of bipolar transistor 110. In this manner, the heavily doped bulk provides a mechanism of preventing the positive feedback loop previously described from turning on.
Accordingly, it will be appreciated from the proceeding discussion that to achieve simultaneously the goals of improving the performance characteristics of a CMOS integrated circuit while maintaining adequate immunity to latchup, it is beneficial to provide a starting material that includes a lightly doped region formed over a heavily doped region. The lightly doped region provides a suitable substrate for the formation of complimentary and relatively lightly doped well regions desirable for the fabrication of high speed integrated circuits. The heavily doped bulk portion of the starting material provides the necessary low impedance path required for addressing and improving latchup immunity. It will be further appreciated to those skilled in the art of CMOS semiconductor fabrication that, for a large percentage of integrated circuit applications, it is desirable if the starting material is doped p-type. Thus a suitable starting material commonly found in CMOS semiconductor fabrication facilities includes a lightly doped p-type layer formed over a heavily doped p+ layer. Maximum immunity to latchup is obtained when the lightly doped upper region of the starting material is as shallow as possible. Unfortunately, the relatively high mobility of boron, which is typically used as a p-type impurity in a silicon substrate, places a lower limit on the depth of the lightly doped region of the substrate. Impurities within the heavily doped portion of the starting material may migrate toward the surface of the silicon substrate during high temperature processing undesirably resulting in an increased doping level within the lightly doped region possibly resulting in a redistribution sufficient to render the device inoperable. Furthermore, in addition to concerns about the redistribution of boron atoms within the heavily doped portion of the wafer during subsequent processing, starting material that has the desired lightly doped region formed over a heavily doped region is typically obtained only at a premium over the cost of obtaining uniformly doped starting materials. Accordingly, it would be desirable to provide a starting material alternative for a semiconductor manufacturer that addresses the concerns related to the costs of conventional epitaxial wafers, the problem of up diffusion of boron atoms, and permits the fabrication of heavily doped regions within the starting material in extremely close proximity to the upper surface of the silicon.